The present invention concerns the fabrication of integrated circuits. The invention pertains particularly to reliable processes for forming gates with differing gate oxide thicknesses.
For integrated circuits which utilize 3.3-volt technology, the nominal power supply is at 3.3 volts. The signals can switch between 3.3 volts and 0 volts. When constructing an integrated circuit which uses 3.3-volt technology, it is often desirable that some of the transistors on the integrated circuit be able to tolerate placement of 5-volt signals. Such transistors can be utilized for input/output (I/O) cells of the integrated circuit. When the gate oxide thickness for the 3.3-volt technology cannot support 5-volt operation, a dual gate oxide process is used. That is, the thickness of the gate oxide for transistors in the core of the integrated circuit is thinner than the gate oxide for transistors in the I/O cells of the integrated circuit.
Dual gate oxide fabrication processes generally involve several steps of applying and stripping photoresist and other materials from a substrate surface during formation of gate oxide. Frequently, metals and other contaminants are introduced at the substrate surface during such processing. The contaminants can decrease a lifetime of a transistor formed over the contaminated surface. Accordingly, it is desirable to develop cleaning processes which can remove metals and other contaminants from a substrate surface, and to apply such cleaning processes to dual gate oxide fabrication processes.